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(scroll down near the bottom of the linked article) about AMD’s upcoming EPYC “Rome” generation of EPYC server processors. The main point is that users will be able to buy up to () on a single packaged processor. This increase in core count will likely be due to the process node shrink, from 14nm down to GlobalFoundries’ . This as the upcoming second-generation Zen processors, which are built on and expected to ship in a few months. Rome is probably not coming until. But … up to. Also, if I’m understanding WCCFTech’s post correctly, AMD will produce for this product line. One design will have per die (x4 for 48 cores per package) and the other will have per die (x4 for 64 cores per package). The reason why this is interesting is because AMD is, apparently, expecting to sell enough volume to warrant multiple chip designs, rather than just making a flagship and filling in SKUs with bin sorting and cutting off the cores that require abnormally high voltage for a given clock rate as parts with lesser core count. (That will happen too, as usual, but from two different intended designs instead of just the flagship.) If it works out as AMD plans, this could be an opportunity to acquire prime market share away from Intel and their Xeon processors. The second chip might let them get into second-tier servers with an even more cost-efficient part, because a 12-core die will bin better than a 16-core one and, as mentioned, yield more from a wafer anyway. Again, this is a common practice from a technical standpoint; the interesting part is that it could work out well for AMD from a strategic perspective. The timing and market might be right for EPYC in various classes of high-end servers.
