AMD’s Lisa Su introduced the company’s latest innovation during her Computex 2021 keynote: 3D V-Cache. Does it point to the future of processor innovation?
AMD made some news last night during its Computex 2021 keynote address when AMD CEO Dr. Lisa Su showed off the company’s new 3D chiplet technology, developed in partnership with TSMC. The long and short of it is that rather than spread itself out over a wider die, CPU components like the logic unit and cache memory are stacked on top of each other, utilizing vertical space rather than growing the total surface area of the chip in a flat wafer. While the technology is primarily being pioneered by TSMC, AMD looks to be the first chipmaker to take advantage of the new process by introducing new “vertical L3 cache” to its Ryzen series processors. Without getting bogged down too much in computer system architecture, cache memory is the part of the processor that stores the most relevant data and program instructions for the processor at any given time. The larger the cache, the more data can be stored there so the processor doesn’t have to fetch new data from RAM, which takes longer and slows down performance. According to Su, by stacking a 64MB SRAM node onto the CCD (the part of the processor that contains a collection of processing cores), AMD is able to triple the available L3 cache on a 16-core processor from a maximum of 64MB to 192MB.
