The death of Intel’s ‘Tick-Tock’ means that Kaby Lake is Intel’s third crack at their 14nm process. 14nm started with Broadwell (5 th Gen, tick), introduced a new microarchitecture with Skylake (6 th Gen, tock), and now is in the ‘optimization’ stage with Kaby Lake (7 th Gen). This means an improved ‘14nm Plus’, offering better power efficiency and higher frequencies through a less strained transistor floorplan. Intel is launching a myriad of SKUs under Kaby Lake, ranging from mobile KBL-U at 15W and 28W through mobile KBL-H at 45W and desktop-class KBL-S at 35W to 91W. This includes three overclocking SKUs for desktop, including an i3 variant. Here’s the front page of AnandTech’s Kaby Lake launch coverage.
Despite what has been released elsewhere on the internet, today marks the second official launch of Kaby Lake, the first being back in September with six mobile processors which currently feature in the premium notebook and mini-PC categories. As a ‘trial run’, these six processors have shown promise and as a result another 25+ are coming to the wider market.
The main features for Kaby Lake includes support for Optane Memory, a range of new 200-series chipsets to support the processors, an update to the Gen9 graphics featuring Main10 support and other lower power hardware accelerated video playback, as well as adjustments to the underlying silicon to afford a better voltage frequency curve.
Intel’s ‘Tick-Tock’ cadence has disappeared, as we’ve reported on several times previously, and Kaby Lake is the first wave of Intel’s ‘Optimization’ step in their ‘Process, Architecture, Optimization’ release structure. The goal of the first two steps in that trio have been well documented over the last decade or so of Intel releases: a process change means a shrink in the minimum feature size of the silicon (and arguably represents the main business focus of Intel’s R&D), such as from 90nm to 65nm or 22nm to 14nm, and ‘architecture’ indicates an improvement to the underlying microarchitecture, typically taking advantage of the new process in the previous step. Both of these steps, barring a significant paradigm shift in the microarchitecture, have yielded 5-15% performance jumps each iteration. Also, based on yield, typically the smaller chips are the ones to come to market first.
The Optimization step is a relative unknown, as the term is somewhat definable in many different contexts when it comes to semiconductor design. Optimization could be an adjustment to the base microarchitecture giving it more support, or an adjustment in the silicon manufacturing process giving better efficiency, or it could be a different set of SKUs for a changing market, or it could be an updated internal graphics implementation. There are many ways in which Intel could play the optimization card, and for the launch of their 7 th generation processors, it comes across as a number of features.
At this point I should mention the Devil’s Canyon launch of the i5-4690K and i7-4790K, which were out-of-cycle launches of new overclocking products. While Intel marketed this as an ‘optimization’ of the current design, it technically wasn’t part of the PAO cadence. Most of the Devil’s Canyon optimization was around heat management rather than any other significant shift, whereas the ‘Optimization’ label for Kaby Lake is an actual physical change to the silicon.
