CEO reveals new Teslas include AMD silicon and that Samsung has signed to pack RDNA 2 graphics into Exynos SoCs
COMPUTEX AMD has revealed a new 3D chip stacking technology it claims delivers the equivalent performance boost to a new generation of chip architecture. The new tech was revealed in a keynote address to the virtual Computex exhibition delivered by AMD president and CEO Doctor Susan Lu, who said the tech bonds “64MB of 7nm SRAM cache directly onto each core complex, effectively tripling the amount of cache feeding our Zen3 cores.” Signals and power pass across silicon, and Lu said the result is more than 2TB/s of bandwidth with superior thermal performance, a 200x improvement in interconnect density and 15 times better density than other chip stacking technologies. AMD’s approach to stacking uses a direct copper-to-copper bond, instead of silicon microbump tech used by other players. One result of this approach, Lu said, is that AMD uses a third of the energy required by rivals. Lu said the tech is currently targeted at gaming and will go into production on AMD’s highest end products by the end of 2021.
